DRAM chips; built-in self test; integrated circuit testing; design for testability; large scale integration; cache storage; programmable logic arrays; logic testing; SRAM chips; functional BIST; DFT; design for test; BIST engine; embedded DRAM cache LSI; SRAM macros; programmable logic arrays;
机译:具有速度可扩展设计和可编程全速功能阵列BIST的750MHz 144Mb高速缓存DRAM LSI
机译:具有速度可伸缩设计和可编程函数阵列BIST的750MHz 144MB缓存DRAM LSI
机译:用于嵌入式DRAM的可编程BIST内核
机译:可编程的AT-SCEED阵列和嵌入式DRAM LSI的功能BIST
机译:功能分解有限域乘法器,以在现场可编程门阵列上高效实现。
机译:现场可编程门阵列嵌入式平台用于动态肌肉纤维传导速度监测
机译:用于嵌入式DRam LsI的可编程高速阵列和功能BIsT