A novel layout scheme of array cell (AC) architecture is described, which is dedicated to low-power NMOS 4-phase dynamic logic. An AC is constructed of (M x N)+2 transistors so as to constitute each type of NMOS 4-phase logic gates. A graph theoretic approach together with a simulated annealing algorithm is exploited in the layout design of the AC to pursue for the area reduction. A number of experimental results demonstrate the practicability of the proposed approach.
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机译：描述了一种新颖的阵列单元（AC）架构布局方案，该方案专用于低功耗NMOS 4相动态逻辑。 AC由（M x N）+2个晶体管构成，以构成每种类型的NMOS 4相逻辑门。在交流电的布局设计中，采用了图论方法和模拟退火算法，以求减小面积。许多实验结果证明了该方法的实用性。
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