New approach to mask and wafer performance optimization for System on a Chip (SOC) devices

摘要

Detection of reticle CD errors appears to be one of the most critical challenges for low-k1 lithography, where CD accuracy, as Mean-to-Nominal and Mask Error Factor determine most of wafer CD budget. Measurements of reticle CD's are always a difficult process, as the mask manufacturer need to know the critical areas on the masks where he has to execute the measurements. This information is not generally available and if it is available, the number of measuremnts can be extremely large, in particular for System-On-a Chip devices with multiple critical areas resulting from the multiple electrical functions located on the chip.