A study of fully silicided 0.18um CMOS ESD protection devices

摘要

We studied the optimization of the ESD protection circuit based on the test results of MM and HMB by using the TEG created in the fully silicided 0.18um CMOS process. We concluded that the change in drain area and channel width had different effects on the ESD robustness of different test itmes because the type of an operating ESD protection element was determined by the polarity of the ESD surge applied. In addition, we found that, by the formation of silicides in a source and drain contact, the dimensions around the contact had a less influence on the ESD robustness and the channel width had a large influence on the ESD robustness.