Influence of gate length on ESD-performance for deep sub micron CMOS technology

摘要

ESD-performance of grounded-gate nMOS protection structures has been observed for a standard 0.25 mu m CMOS epitaxial layer based technology. The shortest gate lengths show unepectedly lower ESD-thresholds, leading to an optimum performance for longer gate length devices attributed to the trade off between power dissipation and melt volume of the parasitic bipolar.