The SOI technologies presented here use selective epitaxial growth (SEG) and epitaxial lateral overgrowth (ELO) of silicon to create device sized SOI islands in multiple layers to achieve 3-D integration. SOI device islands were fabricated with sizes from 0.15#mu# X 0.15#mu#m to 8 #mu#m X 500 #mu#m, with thickness from 40 nm to 200 nm. Deepsubmicron FD-SOI P-MOSFETs, with measured gate lengths down to L_(eff)=0.1 #mu#m, were fabricated in the first and second layer SOI islands to demonstrate device material quality. The off-state leakage currents were less than 0.2 pA/#mu#m. The measured subthreshold behavior of a typical W = 5#mu#m and L_(eff) = 0.25 #mu#m FD-SOI P-MOSFET had a subthreshold swing of 76 mV/dec, leakage below 0.2 pA/#mu#m with I_(D,sat) of 146 #mu#A/#mu#m and a threshold voltage of -0.103 volts. FD-SOI P-MOSFETs in the second layer had similar results.
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机译：本文介绍的SOI技术使用硅的选择性外延生长（SEG）和外延横向过生长（ELO）来在多层中创建器件尺寸的SOI岛，以实现3-D集成。制造的SOI器件岛的尺寸为0.15＃mu＃X 0.15＃mu＃m至8＃mu＃m X 500＃mu＃m，厚度为40 nm至200 nm。在第一和第二层SOI岛中制造了测量到的栅极长度低至L_（eff）= 0.1＃mu＃m的深亚微米FD-SOI P-MOSFET，以证明器件的材料质量。截止状态的泄漏电流小于0.2 pA /＃mu＃m。典型的W = 5＃mu＃m和L_（eff）= 0.25＃mu＃m的实测亚阈值行为FD-SOI P-MOSFET的亚阈值摆幅为76 mV / dec，泄漏低于0.2 pA /＃mu＃m I_（D，sat）为146＃mu＃A /＃mu＃m，阈值电压为-0.103伏。第二层中的FD-SOI P-MOSFET具有相似的结果。
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