3-D SOI Using Epitaxial Lateral Overgrowth

摘要

Silicon-on-insulator (SOI) wafers are capable of pro-ducing low-power, low-voltage devices, essential for scaling gates to below 100 nm. But to achieve gigahertz speed and 10~(12) transistors per die, 3-dimensional integration may be necessary to decrease interconnect lengths that impede speed. One approach is 3-D SOI technology — fabrication of devices in alternating layers of silicon separated by an insulator. For example, PMOS could be on one SOI level and NMOS on a second level with several layers of metal interconnections. The result is a reduction in interconnect lengths from microns to less than tenths of microns, thus decreasing resistance and capacitance, increasing speed, and reducing the circuit footprint.