A 180 nm-generation flash memory technology has been developed, optimized for small cell size, high performance low voltage operation and multi-level-cell and embedded logic capability. Memory cell scaling utilizes scaled trench isolation, self-aligned floating gates, cobalt salicided complementary poly gates, unlanded contacts and traditional dielectric and junction scaling. Low voltage performance is achieved with the inclusion of logic compatible NMOS and PMOS transistors, a triple well and 3 layers of metal interconnect. 16 Mbit flash memories with 0.38 /spl mu/m/sup 2/ cell size have been built on this technology as a yield and reliability test vehicle.
展开▼
机译：已经开发了一种180纳米的闪存技术，该技术已针对小单元尺寸，高性能低压操作以及多级单元和嵌入式逻辑功能进行了优化。存储器单元缩放利用缩放的沟槽隔离，自对准浮置栅极，硅化钴互补多晶硅栅极，未着陆触点以及传统的介电和结缩放。包括逻辑兼容的NMOS和PMOS晶体管，三重阱和3层金属互连，可实现低电压性能。在这项技术上已经构建了具有0.38 / spl mu / m / sup 2 /单元大小的16 Mbit闪存，作为成品率和可靠性测试工具。
展开▼
