Most of path enumeration-based timing analysis tools use a single delay per gate for path delay calculation. However, the timing analysis of current submicron designs demands more accurate delay calculation methods, which can improve path enumeration accuracy and especially, critical delay estimation accuracy. This paper presents modifications to the classical best-first procedure proposed by Yen et al. (1989) in order to consider a pair of delays per gate. The increase in the accuracy of path delay calculation is evaluated by running both the original and the improved path delay calculation methods on the ISCAS'85 circuits.
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