In the high-speed digital printed circuit board (PCB), there exists a layer capacitance (generally from 0.02 nF to 200 nF) between the closely spaced power and ground layers, which has some restriction on delta-I noise. According to the MPIE (mixed potential integral equation), a model is developed to analyze and characterize quantitatively the restriction on delta-I noise by the power/ground structure in PCB in high frequencies (from 100 MHz to 3 GHz). In comparison with the measured data from a testboard, the method produces relatively precise results. The restriction on delta-I noise is complicated by the high frequency and several strategies are provided to reduce the noise.
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