Re-use-centric architecture for a fully accelerated testbench environment

摘要

This paper presents a new technology that accelerates functional system verification. Starting with a behavioral testbench, we developed a seamless flow to generate a re-use-oriented architecture for a synthesizable testbench without losing compatibility with the original testbench. Consequently, we combine the flexibility of a behavioral testbench and the simulation performance of a synthesizable testbench, while greatly reducing the modeling overhead. The approach itself is hardware independent. To prove the usability of our approach, we verified a hard disc controller on an emulator. With this setup, we achieved a speed-up factor of 5000 versus plain simulation.