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Design of the DSSL Testbench Hardware Architecture for Rapid Development and Execution of Hardware-in-the-Loop Control

机译：快速开发和执行硬件在环控制的DSSL Testbench硬件体系结构设计

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作者
Chu, Clayton;
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作者单位

University of Washington;

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授予单位 University of Washington;
学科
学位 M.S.A.A.
年度 2012
页码 117 p.
总页数 117
原文格式 PDF
正文语种 eng
中图分类
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入库时间 2022-08-17 11:56:17

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Design of the DSSL Testbench Hardware Architecture for Rapid Development and Execution of Hardware-in-the-Loop Control

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