A 0.1-/spl mu/m double-deck-shaped gate HJFET with reduced gate-fringing-capacitance for ultra-high-speed ICs

摘要

This paper describes a novel double-deck-shaped (DDS) gate technology for 0.1-/spl mu/m heterojunction-FETs (HJFETs) that have half the external gate fringing capacitance (C/sub f//sup ext/) of conventional T-shaped gate HJFETs. By introducing a T-shaped SiO/sub 2/-opening technique based on two-step dry-etching with W-film masks, we have fabricated 0.1-/spl mu/m DDS gate-openings adapted to the reduction in C/sub f//sup ext/ and to the voidless-filling of gate-metals. Moreover, by using WSi-collimated sputtering and electroless Au-plating, 0.1-/spl mu/m DDS WSi/Ti/Pt/Au gate HJFETs with high uniformity and reproducibility are made. Fabricated n-Al/sub 0.2/Ga/sub 0.8/As-In/sub 0.15/Ga/sub 0.75/As HJFETs exhibit an excellent V/sub th/ standard-deviation (/spl sigma/V/sub th/) of 39 mV. Also, the HJFET covered with a SiO/sub 2/ film shows a very high millimeter-wave performance with f/sub T/ of 120 GHz and f/sub max/ of 165 GHz, due to the low C/sub f//sup ext/. In addition, a high f/sub T/ of 151 GHz and f/sub max/ of 186 GHz are obtained without a SiO/sub 2/ film.