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A multichip package for high-speed logic die

机译:用于高速逻辑芯片的多芯片封装

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摘要

An attempt to develop a multichip module infrastructure is reported. Design, assembly, and test methodologies were developed and implemented. Several prototype modules were fabricated to accommodate six flip chip mounted 463 I/O H4C 123 gate array logic die. These modules were used as test vehicles to verify the effectiveness of the development infrastructure.
机译:报告了开发多芯片模块基础设施的尝试。开发,实施了设计,组装和测试方法。制造了几个原型模块,以容纳六个倒装芯片安装的463 I / O H4C 123门阵列逻辑芯片。这些模块用作测试工具,以验证开发基础结构的有效性。

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