In complex circuits the test execution is usually divided into a number of subtasks, each producing a signature in a self-test register. These signatures influence one another. A model that can be used as a basis for test scheduling procedures is presented, and it is shown how test schedules can be constructed, in order to minimize the number of signatures to be evaluated. The error masking probabilities decrease when the subtasks of the test execution are repeated in an appropriate order, and an equilibrium situation is reached where the error masking probabilities are minimal. A method is presented for constructing test schedules so that only the signatures at the primary outputs must be evaluated to get a sufficient fault coverage. Then no internal scan path is required, only a few signatures have to be evaluated at the end of the test execution, and the test control at chip and board level is simplified. The amount of hardware to implement a built-in self-test is reduced significantly.
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