Efficient improvement of hot-carrier-induced degradation for sub-0.1 μm CMOSFET

摘要

The effect of post-thermal annealing (PA) after halo implantation on the reliability of sub-0.1 μm CMOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot-carrier-induced device degradation. The best results of device performance were obtained with post-annealing treatment performed at medium temperatures for a longer time.