A Highly Robust Double Node Upset Tolerant latch

摘要

Due to technology scaling, radiation induced errors which cause a double node upset (DNU) have become more common in data storage elements. All current designs either suffer from high area and performance overhead or are vulnerable to an error after a DNU thus making them unsuitable for clock gating. A novel latch design is proposed in which all internal and external nodes are capable of recovering the previous value after a single or double node upset. The proposed latch offers higher speed, lower power consumption and lower area requirements compared to all existing DNU tolerant latches capable of recovering all nodes.