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Effect of In-situ Capping on Phase Change Memory Device Performance : AEPM: Advance Equipment Processes and Materials

机译:原位封盖对相变存储设备性能的影响:AEPM:先进的设备工艺和材料

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Oxidation of phase-change memory (PCM) materials (e.g. $Ge_{2}Sb_{2}Te_{5}$, GST) has been shown to decrease crystallization temperature and impact film composition, thus impacting analog switching behavior [1], [2]. PCM mushroom-cell devices were engineered on a 14 nm backend test vehicle to compare the electrical switching performance of in-situ and ex-situ capped GST 225. To mitigate the electrical effects from varying top electrode processes between tools, in-situ devices were fabricated with a Ti-TiN cap on GST before exposure to air. The in-situ cap is reduced to a minimal thickness to prevent oxidation of the Ti adhesion layer and the remainder of TiN was deposited matching to the ex-situ top electrode process. TEM of in-situ capped samples were found to have less GST undercut from patterning and have less reduction of the contact area between the GST and top electrode. SET and RESET programming of in-situ capped PCM devices show comparable SET and RESET state resistances to ex-situ processed PCM devices. Current-voltage measurements show that the in-situ PCM can have slightly lower voltage threshold switching but achieves a significantly higher current after threshold switching. The increased current for in-situ capped PCM results in higher power consumption with fixed voltage programming.
机译:已经证明,相变存储(PCM)材料(例如$ Ge_ {2} Sb_ {2} Te_ {5} $,GST)的氧化会降低结晶温度并影响薄膜成分,从而影响模拟开关性能[1], [2]。 PCM蘑菇状电池器件是在14 nm后端测试车上设计的,以比较原位和异位加盖的GST 225的电开关性能。为减轻工具之间不同的顶部电极工艺产生的电效应,我们采用了原位器件在暴露于空气之前在GST上用Ti-TiN帽制成。将原位盖减小到最小厚度以防止Ti粘附层氧化,并沉积TiN的其余部分以与原位顶部电极工艺相匹配。发现原位封端的样品的TEM具有较少的图案化GST底切,并且GST与顶部电极之间的接触面积减少较少。原位封盖的PCM器件的SET和RESET编程显示,与异位处理的PCM器件可比的SET和RESET状态电阻。电流电压测量结果表明,原位PCM的电压阈值开关可以稍低一些,但在阈值开关后可获得明显更高的电流。使用固定电压编程时,原位加盖PCM的电流增加,导致功耗更高。

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