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A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture

机译:使用扫描架构的回收IC零成本检测方法

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The recycling of used integrated circuits (ICs) has raised serious problems in ensuring the integrity of today’s globalized semiconductor supply chain. This poses a serious threat to critical infrastructure due to potentially shorter lifetime, lower reliability, and poorer performance from these counterfeit new chips. Recently, we have proposed a highly effective approach for detecting such chips by exploiting the power-up state of on-chip SRAMs. Due to the symmetry of the memory array layout, an equal number of cells power-up to the 0 and 1 logic states in a new unused SRAM; this ratio gets skewed in time due to uneven NBTI aging from normal usage in the field. Although this solution is very effective in detecting recycled ICs, its applicability is somewhat limited as a large number older designs do not have large on-chip memories. In this paper, we propose an alternate approach based on the initial power-up state of scan flip-flops, which are present in virtually every digital circuit. Since the flip-flops, unlike SRAM cells, are generally not perfectly symmetrical in layout, an equal number of scan cells will not power-up to 0 or 1 logic states in most designs. Consequently, a stable time zero reference of 50% logic 0s and 1s cannot be used for determining the subsequent usage of a chip. To overcome this key limitation, we propose a novel solution in this paper that reliably identifies used ICs from testing the part alone, without the need for any additional reference data or even the netlist of the circuit. Through scan testing of the IC, we first identify a significant number of asymmetrically stressed flip-flops in the design, divided into two groups. One group of flip-flops is selected such that it mostly experiences the 1 logic state during functional operation, while the other group mostly experiences the 0 state. The resulting differential stress during operation causes growing disparity over time in the number of 0s (and 1s) observed in these two groups at power-up. When new and unaged, these two groups behave similarly, with similar percentage of 1s (or 0s). However, over time the differential stress makes these counts diverge. We show that this changing count can be a measure of operational aging. Our simulation results show that it is possible to reliably detect used ICs after as little as three months of operation.
机译:废旧集成电路(IC)的回收在确保当今全球化的半导体供应链的完整性方面提出了严重的问题。由于这些伪造的新芯片可能会缩短使用寿命,降低可靠性并降低性能,因此对关键基础架构构成了严重威胁。最近,我们提出了一种通过利用片上SRAM的上电状态来检测此类芯片的高效方法。由于存储器阵列布局的对称性,在新的未使用的SRAM中,相等数量的单元加电至0和1逻辑状态。由于NBTI在现场正常使用导致老化不均匀,因此该比率在时间上出现了偏差。尽管此解决方案在检测回收的IC方面非常有效,但由于许多较旧的设计没有大容量的片上存储器,因此其适用性受到一定限制。在本文中,我们提出了一种基于扫描触发器的初始加电状态的替代方法,该方法几乎存在于每个数字电路中。由于与SRAM单元不同,触发器通常在布局上不是完全对称的,因此在大多数设计中,相等数量的扫描单元将不会加电到0或1逻辑状态。因此,不能使用逻辑为0和1为50%的稳定时间零基准来确定芯片的后续使用。为了克服这一关键限制,我们在本文中提出了一种新颖的解决方案,该解决方案可以通过单独测试零件来可靠地识别出使用过的IC,而无需任何其他参考数据,甚至不需要电路网表。通过对IC的扫描测试,我们首先确定设计中有大量不对称受压的触发器,分为两组。选择一组触发器,使得它在功能操作期间大部分经历1逻辑状态,而另一组大多数经历0状态。在操作过程中产生的差异应力会导致随着时间的推移,在上电时在这两组中观察到的0s(和1s)数量之间的差异越来越大。当新的和未老化的时,这两组的行为相似,具有相似的1s(或0s)百分比。但是,随着时间的流逝,压差使这些计数发散。我们表明,这种变化的计数可以衡量运营老化。我们的仿真结果表明,仅需运行三个月,就可以可靠地检测出用过的IC。

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