A Low-Power 10-bit 160-MSample/s DAC in 40-nm CMOS for Baseband Wireless Transmitter

摘要

A low-power 10-bit 160-MSample/s digital to analog converter (DAC) for baseband wireless transmitter is proposed and demonstrated. The design considerations of architecture and floorplan have been discussed, aiming to minimize power consumption without degradation of static linearity and spurious free dynamic range (SFDR). An optimized layout reduces parasitic and mismatch effects. The simulation result shows that the SFDR is more than 70 dB (67 dB) for input signals up to 8.75 MHz (70 MHz) and the power consumption is 0.43 mW with a 1.1 V power supply. The proposed DAC has been verified in 40-nm CMOS and has an active area of 0.036 mm².