Exploring the Electrical Behavior of High-K Triple-Material Double-Gate Junctionless Silicon-on-Nothing MOSFETs

摘要

As semiconductor devices advance to sub-45 nm range, there has been a great deal of development in the device area along with some critical issues. One such issue is the decrease in device threshold voltage which is due to a decrease in control by the gate upon the channel region and an increase in drain/source charge sharing. This case is generally termed as short channel effects (SCEs). In this paper, a study is demonstrated to reduce the said effect on a junctionless silicon-on-nothing (SON) double-gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) by fusing the idea of multi-material gate technology and high dielectric oxide technique. This paper presents the analysis of significant device parameters such as potential and the threshold voltage of the proposed device built on ATLAS simulations data. A comparison with other device structures is also carried out. The effects on changes in various device parameters are also studied.