Low Power 16 Phase Ring Oscillator and PLL for Use in sub-ns Time Synchronization over Ethernet

摘要

A 16 Phase Ring Oscillator and phase locked loop (PLL) suitable for time synchronization with down to 500 ps accuracy via Fast Ethernet is presented. To reduce power consumption a new buffer stage known from CMOS level shifters is proposed. The power consumption of the output buffer is important for such applications where all clock phases are outputted and used for synchronization. The PLL is fabricated in a low cost 180 nm technology from GlobalFoundries and achieves a RMS jitter of 3.2 ps at 125 MHz while consuming only 6.1 mW including all bias circuitry and output drivers.