High SFDR Pipeline ROM-less DDFS Design on FPGA Platform Using Parabolic Equations

摘要

A 4-stage pipeline ROM-less direct digital frequency synthesizer (DDFS) with equal division interpolation is proposed in this work. To attain higher SFDR (spurious free dynamic range) and faster clock rate, the hardware cost and delay using different segments with various interpolation equations are analyzed systematically to explore the optimal solution. The parabolic equations with proper selection of coefficients and factorized operation orders based on optimized hardware cost and delay are finally utilized to enhance SFDR. The proposed design is demonstrated by the physical implementation on Altera FPGA platform. The average SFDR is measured to be 68.4242 dBc with 1.1659 dBc deviation over 33 times of experiments. The measured SFDR is proved to outperform many previous DDFS works even if they were implemented on silicon.