High Efficient Modulo 2~n-2~k-1 Adder VLSI Design and Implementation for RNS

摘要

The design of high efficient modulo adders is important for the implementation of DSP algorithms based on Residue Number System (RNS). Moduli sets with this form 2~n-2~k-1 offer many advantages, such as larger dynamic range and excellent balance among the RNS channels. In this paper, a general algorithm and its VLSI implementation structure are proposed for modulo 2~n-2~k-1 adder. The proposed algorithm is based on the techniques of prefix operation and carries correction, which eliminates the re-computation of carries. And any existing prefix operation structure can be adopted in the proposed structure. Compared with the same modulo adders with different structures, the proposed modulo 2~n-2~k-1 adder offers better area*delay.