Energy efficient analog spiking temporal encoder with verification and recovery scheme for neuromorphic computing systems

摘要

Making a computing system that mimic biological neural behavior in mammalian brain has attracted worldwide attention and endeavor. Neuromorphic computing systems, employing very-large-scale integration circuits to implement onto hardware, incorporates learning. Neural encoder, as one of the crucial component in neuromorphic computing systems, encodes the input information into spikes. By taking the temporal response structure into consideration, temporal encoding with interspike intervals exhibits the capability of containing more information and encoding information using the time correlation between spikes. In this paper, a neural encoder with iterative structure, adapting interspike interval encoding scheme, is proposed. Considered the tradeoff between power consumption and die area, we employed an analog implementation of the spiking neuron. By doing so, power-consuming analog-to-digital converters (ADCs) and operational amplifiers (Op-AMPs) are not needed, resulting in a tremendous saving on power consumption and die area. Due to the iterative processing, the growth of the spike amounts with respect to the neuron number is exponential, which significantly reduces power consumption.