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Highly efficient chip scale package (CSP) LED based on surface patterning

机译:基于表面图案化的高效芯片级封装(CSP)LED

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Surface patterning, in terms of microstructure, as a precise surface roughness method for chip scale package (CSP) LED, will enormously improve the light extraction efficiency (LEE) with much less total internal reflection loss. In this paper, several kinds of microstructures and layouts have been designed and optimized by using the Monte Carlo ray-tracing simulation method. During the simulation, an accurate CSP-LED model is built Shape, size, separation and arrangement of the microstructures are taken into consideration to find out how much the above parameters affect the LEE. LEE Enhancement of more than 20% is achieved by several structures compared to CSP-LED without surface patterning. Among which, enhancement of 20.90% is reached utilizing 5×5 pyramid arrays with a gradient of 54.7 degrees. Furthermore, each designed microstructure is also fabricated through the nano-imprint technology. Experimental results prove the feasibility of former designs and 20.31% enhancement of LEE is achieved.
机译:就微结构而言,表面图案化作为芯片级封装(CSP)LED的一种精确的表面粗糙度方法,将极大地提高光提取效率(LEE),而总内部反射损耗却少得多。本文使用蒙特卡洛射线追踪模拟方法设计并优化了几种微结构和布局。在仿真过程中,建立了一个精确的CSP-LED模型,并考虑了微结构的形状,大小,分离和排列,以找出上述参数对LEE的影响程度。与不带表面图案的CSP-LED相比,几种结构可以使LEE增强20%以上。其中,利用5×5金字塔阵列以54.7度的梯度达到20.90%的增强。此外,还通过纳米压印技术来制造每个设计的微结构。实验结果证明了先前设计的可行性,并实现了LEE的20.31%的提高。

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