Mechanism and improvement of breakdown degradation induced by interface charge in UHV device

摘要

This paper presents an innovative p-top engineering to simulate and optimize the breakdown degradations in different regions of the interdigitated layout such as source center(SC), drain center(DC), and flat region of an Ultra high voltage(UHV) device. In manufacturing of UHV device, breakdown voltage degradation takes place due to interface charges, current crowding and breakdown degradation was also observed at wafer-stage with temperature stress resulted from package level reliability tests. Optimizations are done to sustain high breakdown voltage by varying the p-top mask design to investigate the interface charge effect on breakdown. ESD test is also conducted to show the difference in interface charges after stress. A better stability has been obtained for maximum p-top length structure with respect to breakdown and ESD testing.