This paper presents the methods required to implement a high speed and high performance parallel complex number multiplier. The designs are structured using Radix-4 Modified Booth Algorithm and Wallace tree. These two techniques are employed to speed up the multiplication process as their capability to reduce partial products generation to η/2 and compress partial product term by a ratio of 3:2. Despite that, carry save-adders (CSA) is used to enhance the speed of addition process for the system. The system has been designed efficiently using VHDL codes for 16×16-bit signed numbers and successfully simulated and synthesized using ModelSim XE II 5.8c and Xilinx ISE 6.1i. As a proof of concept, the system is implemented on Xilinx Virtex-II Pro FPGA board.
展开▼
机译：本文介绍了实现高速和高性能并行复数乘数所需的方法。设计使用基数-4修改展位算法和华莱士树构造。使用这两种技术来加速乘法过程作为其能力，以将部分产品减少到η/ 2并压缩部分产品期限为3：2的比例。尽管如此，携带保存加法器（CSA）用于增强系统的加法速度。系统已经使用VHDL代码有效地设计了16×16位符号数，并使用Modelsim XE II 5.8C和Xilinx ISE 6.1i成功模拟和合成。作为概念证明，系统在Xilinx Virtex-II Pro FPGA板上实现。
展开▼
