Motivated by reduction of computational complexity, this work develops a pipelined adaptive filter architecture using the sign-error least mean square (LMS) algorithm. The calculation consumed for the proposed algorithm was less than half of the conventional architectures. Besides, the proposed designs derived by retiming technique and with low latency also provide a faster convergence and a higher throughput than those of the delayed LMS (DLMS) algorithm. Using the proposed algorithm, we have designed two different fine-grained pipelined structures compared to the existing ones. In order to reduce latency of the circuits, we use multiple-input addition algorithm to optimize the architecture with less hardware.
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