Clock Domain Imbalances and Their Impact on Test Architecture

摘要

Clock architecture in digital designs goes through an iterative cycle of timing analysis, routing and placement and fixes to meet timing. At a higher level, each of these steps must be done in different scenarios for example: test mode and functional mode. There can be multiple test modes also. There can be many functional clocks in the design adding to the complexity. Each functional clock can spread in multiple directions to different portions of the logic. When the same clock source fans out in multiple directions, depending on the design requirements, all the different legs of the clock may have to be synchronous to each other. Making them synchronous improves testability but functionally they may not have to be synchronous. In such a situation, if a manufacturing defect causes the different legs of the same clock to not be synchronous, the devices will fail the tests when in reality such parts may still meet the functional specification. We propose a design technique to generate quality tests that takes the above scenario into account such that the manufacturing yield can be improved.