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Testing system for integrated circuits including components for receiving clock signals corresponding to different clock domains

机译:集成电路的测试系统,包括用于接收对应于不同时钟域的时钟信号的组件

摘要

A system for testing an integrated circuit including components for receiving clock signals corresponding to different clock domains includes a pin of the integrated circuit to receive a test clock signal for components included in different clock domains, clock gating cells integrated in the integrated circuit to direct said test clock signal from the pin towards components included in respective clock domains and, coupled to each of the gating cells, a dedicated flip-flop for a respective clock domain, the dedicated flip-flop being also integrated in the integrated circuit to effect on the cell to which it is coupled a clock gating function during testing of the integrated circuit.
机译:一种用于测试集成电路的系统,该系统包括用于接收与不同时钟域相对应的时钟信号的组件,该集成电路的引脚包括用于接收针对在不同时钟域中包括的组件的测试时钟信号的时钟,集成在集成电路中的时钟门控单元将所述时钟门控单元导通。从引脚到包括在各个时钟域中的组件的测试时钟信号,并且耦合到每个选通单元的用于各个时钟域的专用触发器,该专用触发器还集成在集成电路中,以影响在集成电路测试期间,与之耦合的时钟门控功能的单元。

著录项

  • 公开/公告号US8788895B2

    专利类型

  • 公开/公告日2014-07-22

    原文格式PDF

  • 申请/专利权人 NELLY FELDMAN;STEFANO CATALANO;

    申请/专利号US201113050611

  • 发明设计人 NELLY FELDMAN;STEFANO CATALANO;

    申请日2011-03-17

  • 分类号G01R31/28;

  • 国家 US

  • 入库时间 2022-08-21 16:02:38

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