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BGA packaging using insulated wire for die area reduction

机译:使用绝缘线进行BGA封装以减少芯片面积

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In conventional wire bonded packages, design rules require that individual bond wires not touch each other. Also, handling of bonded units may cause wire disturbance leading to wire short. Insulated wire bonding techniques eliminate this requirement by coating a non conductive layer over the bond wires as shown in Fig.1 and thus, electrical isolation is maintained even after wires physically touch each other [1-2]. The focus of this paper is to leverage the insulated wire-bonding technology for die design implementation efficiency in terms of improving electrical parameters and die size reduction. Two specific implementation are discussed in this paper. One is to implement off-chip decoupling capacitor and use it to replace on-die capacitors required for signal integrity and save precious silicon area. Second implementation is about realizing mesh type power grid to improve the IR drop and simultaneously get rid of multiple Power/Ground pads and thus, save silicon area.
机译:在常规的引线键合封装中,设计规则要求各个键合线不能相互接触。另外,操作键合单元可能会引起导线干扰,从而导致导线短路。绝缘线键合技术通过在键合线上覆盖一层非导电层,从而消除了这一要求,如图1所示,因此,即使在线彼此物理接触之后,仍可保持电气隔离[1-2]。本文的重点是在改善电气参数和减小芯片尺寸方面,利用绝缘引线键合技术提高芯片设计的实施效率。本文讨论了两个具体的实现。一种是实施片外去耦电容器,并用它来代替信号完整性所需的片上电容器,并节省宝贵的硅面积。第二种实现方法是实现网状电源网格,以改善IR压降并同时去除多个电源/接地垫,从而节省硅面积。

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