A gate leakage model for double gate tunneling field-effect transistors

摘要

Thinner gate dielectric favors larger drivability of TFETs but also leads to larger gate leakage. In this work, an analytical model is presented to capture the gate leakage current in double gate tunneling FET with ultrathin oxide thicknesses. Its accuracy is verified by TCAD simulations. This gate leakage module has been integrated with our previous TFET model e-TuT and its implications on TFET-based inverters are presented.