Accuracy and speed limitations in DACs across CMOS process technologies

摘要

We present a study of accuracy and timing limitations in current-steering digital-to-analog converters (DACs). Effects of limited output impedance and device mismatches on the DAC performance are discussed and observed for a 10-bit DAC operating at 4 GS/s. These limitations are also studied across 180, 90, and 65 nm CMOS process technologies.