A 12-bit intrinsic accuracy high-speed CMOS DAC

摘要

A 12-bit intrinsic accuracy digital-to-analog (D/A) converternintegrated in a standard digital 0.5 Μm CMOS technology is presented.nIt is based on a current steering doubly segmented 6+2+4 architecturenand requires no calibration, no trimming, or dynamic averaging. Thendifferential nonlinearity (DNL) and integral nonlinearity (INL) are 0.3nand 0.6 least significant bits (LSB's), respectively. The measurednglitch energy is 1.9 pV.s. For a 12-bit resolution, the converternreaches an update rate of 300 MS/s. By reducing the voltage supply ofnthe latches to 2.0 V, the glitch energy is reduced to sub-pV.s, and thenupdate rate reaches 500 MS/s, for a resolution of 8 bits. The worst casenpower consumption is 320 mW, and it operates from a single 3.3 V voltagensupply. The die area is 3.2 mm2