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Low temperature touch down and suppressing filler trapping bonding process with a wafer level pre-applied underfilling film adhesive

机译:低温触摸下降和抑制填充填充粘接过程,用晶片水平预先施加底部填充膜粘合剂

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Flip chip bonding process of the chip touch down at 40°C and suppressing the material trapping at the joint area with the wafer level NCF (Non conductive film), which is pre applied underfilling film adhesive, has been investigated. The test vehicle wafer has 25 μm diameter and 50 μm height bumps which are 10 μm height Cu pillar and 40 μm height Sn-Ag solder cap. The bump pitch was 200 μm. The 55 μm thickness 50 wt% filler loaded NCF was laminated on the wafer and then the surface was planarized with the bump solder layer exposing by the bit cutting technique. Such prepared chip was bonded as the top chip to the bottom chip which has the 25 μm diameter pad of 3 μm Cu bottom, 2 μm Ni middle and 0.1 μm Au top. To insert the sticking step in the bonding process, which melts and flows down the NCF underneath the top chip to the bottom chip partially, the chips were held well the aligned position during the successive processes. The gang bonding possibility was also proved with the four chips together bonding. PCT (pressure cooker test, 121°C and 100%Rh for 168 hours) was performed to the gang bonded samples. By shortening the joint formation step time form 25 to 5 seconds Cu diffusion into the solder bulk area was suppressed and the durable joint to the PCT was formed. It was confirmed by the cross sectional observations.
机译:已经研究了芯片触摸芯片触摸芯片接合处理40°C并抑制在具有晶片水平NCF(非导电膜)的接合区域的材料,该晶片水平NCF(非导电膜)预先涂覆底部填充薄膜粘合剂。试验车晶片直径为25μm,50μm高度凸块,高度Cu柱和40μm高度的Sn-Ag焊料盖。凸起间距为200μm。将55μm厚度50wt%填料加载的NCF层压在晶片上,然后通过钻头切割技术曝光凸块焊料层的表面平坦化。将这种制备的芯片作为顶部芯片粘合到底部芯片上,底部芯片具有25μm的直径为3μmcu底部,2μmni中间和0.1μmau顶部。为了将粘接过程中的粘合过程插入粘合过程,该粘合过程部分地将顶部芯片下方的NCF置于底部芯片下方,芯片在连续过程中保持良好的对准位置。同时还有四个芯片在一起粘合的粘结可能性。对Gang键合样品进行PCT(压力锅测试,121°C和100%RH)进行168小时。通过缩短相对地,将25至5秒的时间形成25至5秒,将Cu扩散抑制到焊料块状区域中,并形成耐用的接头。它被横截面观察确认。

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