A General Co-Design Approach to Multi-Level Package Modeling based on Individual Single-Level Package Full-Wave S-Parameter Modeling Including Signal and Power/Ground Ports

摘要

The power-aware SI (Signal Integrity) simulation takes into account the effect of the power supply noise. It is one of the key issues in the high-speed multi-level package system design. The multi-level package co-design requires a corresponding accurate modeling approach to include all signal, crosstalk and power noise effects to support the poweraware SI simulation. A general co-design approach to multi-level package modeling base on individual single-level package full-wave S-parameter modeling including signal and power/ground ports defined at chip-package and package-board vertical contact arrays is proposed in this paper with three features. Firstly, it includes not only the signal ports, but also the power and ground ports to support the power-aware SI simulations. Secondly, a port in the single-level model by this approach is seamlessly connectable to the corresponding port in another model by virtually connecting not only the port signal terminals, but also the port reference terminals. Thirdly, it combines package DC simulation and high-frequency fullwave simulation to guarantee wide band accuracy. A simple test case of a module-board-module with 20 ports on each module, and 20 ports on the board is used to verify the proposed method by both AC and nonlinear transient simulations. Another simple test case shows that the models by this approach can be used to fully model the transmission line structure in package even in the case of any transmission line referencing.