Design Sensitivity of Single Event Transients in Scaled Logic Circuits

摘要

Single Event Transients (SET) in digital logic pose an ever increasing reliability challenge as device dimensions shrink in modern technologies. Projection of SET sensitivity with scaling is essential to assess the logic failure and error probability in modern technology generations. This paper discusses the effects of device scaling from 45nm to 12nm processes and circuit parameter tuning on SETs. The failure due to particle strikes i.e., Single Event upsets (SEU) as well as its behavior with process variations and reliability mechanisms such as NBTI is evaluated in this work. The critical supply voltage required to avoid SET propagation with circuit parameters is investigated. This work also proposes a probability model which examines the propagation of SET at any node to the output of a circuit. The proposed methodology can be extended to any complex digital circuit to investigate its vulnerability to SET.