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A Weak-Inversion Cmos Analog Multiplier/Divider Circuit

机译:弱反转CMOS模拟乘法器/分频器电路

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摘要

A structure that has a weak-inversion biased MOS transistor at its core which can be used to build analog multipliers, dividers, squarers or square rooters is presented. It relies on the exponential dependence of the drain current to the gate-to-source voltage of a MOS transistor that is biased in the weak-inversion region. The proposed circuit produces at the output a current proportional to the gate-to-source voltage that has, conversely, a logarithmic dependence on the drain current, which is set to be the input current. Given that linear operations in the log-domain correspond to exponentiations, multiplications or divisions in the antilog-domain, the proposed structure serves as a building block for analog multipliers, dividers and many other non-linear circuits.
机译:提出了一种结构,其在其核心处具有弱反转偏置MOS晶体管,其可用于构建模拟乘法器,分隔器,平方体或平方根。它依赖于漏极电流的指数依赖性与在弱反转区域中偏置的MOS晶体管的栅极到源极电压的指数依赖性。所提出的电路在输出时产生与相反地的栅极到源电压成比例的电流对数对数依赖性的电流,该漏极电流被设定为输入电流。考虑到日志域中的线性操作对应于反磁域中的指数,乘法或分割,所提出的结构用作模拟乘法器,分频器和许多其他非线性电路的构建块。

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