TCAD diagnosis of I/O-pin latchup in scaled-DRAM

摘要

This paper describes a TCAD analysis of I/O-pin Latchup failure found in a shallow-well CMOS DRAM. The 0.35/spl mu/m DRAM 1/0-pin showed significant degradation in latchup test of JEDEC Standard over-current stress. TCAD diagnosis of the failure was conducted and newly clarified its biasing effect of guard-band (N+) layer and the layout-related latchup mechanism, which leads to an practical latchup-immunity design in sub-urn CMOS process and layout. To overcome process-margin problem against latchup, a simple CMOS process is proposed for the 0.35/spl mu/m DRAM.