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Study of discrete voids formation in flip-chip solder joints due to electromigration using in-situ 3D laminography and finite-element modeling

机译:采用原位3D灯幕和有限元模拟倒装芯片焊点中离散空隙形成的研究及有限元模拟

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Nowadays, the microelectronics industry broadly uses the flipchip technology to enhance the packaging density. However, the small size and the unique geometry of the flip-chip solder joints induce the electromigration (EM) reliability issue. In this study, a Pb-free solder joints (SAC1205) was EM tested by a current of 7.5×103 A/cm2. During the tests, a three-dimensional (3D) X-ray laminography method was applied to in-situ observe the microstructure evolution. The laminography method allows for the non-destructive observation and provides the quantitative analysis among three dimensions. After EM testing for 650 hr, a new EM failure mechanism was found rather than the well-known models, the pancake void propagation and the under-bump-metallization dissolution. According to the laminography images at different testing stages, many voids simultaneously formed and grew during the entire procedure of testing. Most of them distributed in the current crowding region, but a few also located in the low-current-density region. As the testing time increased, voids grew bigger, coalesced with each other, and finally became large voids which occupied the interface and caused EM failure. The finite-element (FE) method was also applied to analyze the interplay between the microstructure evolution and current density redistribution. A series of 3D FE models were built based on the laminography images at different testing stages. The current density distribution from the FE analysis indicates that the multiple voids formation does not affect the global current density distribution until the voids merged together and became very large voids in the late stage of EM testing. The relieving of the global current crowding in the pancake void model was not found in this new EM failure mechanism. It was the local current crowding found in the new model that responsible for the EM retardation.
机译:如今,微电子工业广泛地使用Flipchip技术来提高包装密度。但是,倒装芯片焊点的小尺寸和独特的几何形状诱导了电迁移(EM)可靠性问题。在该研究中,通过7.5×103a / cm 2的电流测试了无铅焊点(SAC1205)。在测试期间,将三维(3D)X射线晶片流学料方法应用于原位观察微观结构演进。 Laminogruge方法允许非破坏性观察,并在三维之间提供定量分析。在650小时的EM测试后,发现了一种新的EM失效机制而不是着名的型号,煎饼空隙繁殖和凸起金属化溶解。根据不同测试阶段的灯光图象,许多空隙在整个测试过程中同时形成和增长。他们中的大多数分布在当前的拥挤区域中,但是几个也位于低电流密度区域。随着测试时间的增加,空隙较大,彼此合并,并且最终成为占用界面的大空隙并导致EM失败。还应用有限元(Fe)方法来分析微观结构演化和电流密度再分分配之间的相互作用。基于不同测试阶段的Laminogroge图像,构建了一系列3D FE模型。来自Fe分析的电流密度分布表明,在空隙合并的情况下,多个空隙形成不会影响全局电流密度分布,并在EM测试的后期变得非常大的空隙。在这种新的EM失败机制中找不到煎饼缺点模型中的全球当前拥挤的缓解。它是当地目前的拥挤,在新模式中发现,负责EM延迟。

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