Advanced Plasma Doping Technique for USJ

摘要

Fabrication of advanced Logic CMOS devices calls for doping solutions to address requirements for increasingly shallow and abrupt junctions, while maintaining high dopant activation to meet series resistance requirements. VIISta PLAD which has already been adopted in high volume manufacturing in the ultra high dose, low energy regime for advanced DRAM technology nodes, is now being investigated for source drain extension (SDE) implants, where precise and repeatable dopant placement is critical for maintaining control over device parameters. In this article, we investigate the process performance of SDE implants carried out in a VIISta PLAD system using both p- and n-type dopant precursors. Key metrics, such as junction depth, profile abruptness, series resistance, and leakage are reported for as-implanted, as well as samples processed with advanced anneal techniques. The advanced control features in the PLAD system are critical in enabling the process performance required for SDE implants. The intrinsic electrical properties of a field effect transistor are fundamentally dictated by the distribution of electrically active dopants and damage. The concentration of active dopant sets device speed, while junction depth dictates short channel effects. Overlap capacitance, which affects both device speed and power consumption, is determined by dopant distribution in the link-up region [1,2]. With increasingly stringent demands for maximum speed and minimum power consumption at each technology node, increasingly shallow and abrupt source drain extension (SDE) implants, with increasing doses in order to meet series resistance requirements are called for by the ITRS roadmap (Table I). Even though the ITRS guidelines for junction depth and sheet resistance for high performance logic devices have recently been relaxed [3], junctions on the order of 10nm at carrier concentrations of about 5E18 cm~(-3) with sheet resistance values of less than 1000 Ohm/square, and abruptness of less than 2nm/decade will be required soon.