Canonical ordering of instances to immunize the FPGA place and route flow from ECO-induced variance

摘要

Engineering change order (ECO)s for FPGA-based designs often require design changes late in the design process in order to correct functional, timing, and/or technological problems. Typically, after an ECO process a small portion of the circuit netlist is changed. To take advantage of the enormous resources and time already spent on place and route flow, it is desirable to maintain similar post-routing delay characteristics to the pre-ECO stage to avoid further expensive design iterations.