Non-planar surface may cause incorrect transfer of patterns during lithography. In today's IC manufacturing, chemical mechanical polishing (CMP) is used for topographical planarization Since polish rates for metals and oxides are different, dummy metal fills in layout is used to minimize post-CMP thickness variability. Existing metal fill solutions target secondary goals minimizing timing and crosstalk impact. They may however reduce yield by increasing probability of failure (POF) due to particulate defects. Layout design solutions that minimize POF and also improve surface planarity via dummy fill insertions have competing requirements for line spacing. In this work, we present a formulation to balance these competing goals and provide a comparative study of greedy (or fixed spacing), variable spacing and LP formulation based fill insertions based on scalability and quality of solution. Finally, we extend the critical area based solution to include SRAF insertion in order to account for optical diffraction in lithography. The key contributions of this paper are i) layout density analysis model, ii) heuristic greedy, variable spacing and LP formulation based fill insertion techniques and iii) characterization and implementation of inter-feature spacing based SRAF insertion. Thus the proposed solution addresses both lithography and particulate related defects. Experimental results based on layout of ISCAS 85 benchmark circuits show that the variable spacing and the LP formulation based fill insertion techniques result in substantially reduced critical area while satisfying the layout density and uniformity criteria.
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