Recent progress in the fabrication of three-dimensional integrated circuits has opened up the possibility of exploiting this technology to alleviate performance and power related issues raised by interconnects in nanometer CMOS. Physical synthesis for three-dimensional integrated is substantially different from traditional planar integrated circuits due to the presence of additional constraints of placing circuit blocks in multiple die. To realize the full potential offered by three-dimensional integrated circuits, high-level synthesis of these circuits must take layout-related issues unique to 3-D technology into account during the synthesis process. We present a 3-D layout aware binding algorithm for high-level synthesis that tightly integrates the synthesis tasks of resource binding, assignment of modules to multiple die, 3-D floorplanning, and inter-die via minimization. Since floorplanning and resource binding are interdependent, the algorithm can significantly outperform traditional high-level synthesis flows that separate these tasks. Compared to a traditional 3-D layout-unaware binding, experiments show that our approach can improve the total wirelength by 29% on average, while the longest netlength is reduced by 21%. In addition, the number of through-die via count is reduced by 27%. These optimizations are achieved with no penalty in chip area.
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