CMOS inverter delay model based on DC transfer curve for slow input

摘要

This work presents a novel approach to estimate the CMOS inverter delay. The proposed delay model uses the DC transfer curve in order to predict the inverter behavior for slow input transitions rather than estimating the discharging time. Moreover, the only required empirical parameters are those used to calibrate the transistor model. Results are on very good agreement with HSPICE simulations based on BSIM4 transistor model, over a wide range of input slopes and output loads. Comparisons to previously works show that such new delay model offers improved modeling with good trade-off between simplicity and accuracy. The average error is near to 3%, and the worst case error is smaller than 10%.