A Reconfigurable Asynchronous SERDES for Heterogenous Chiplet Interconnects

摘要

With advancing packaging technologies, multi-die integration is gaining prominence among players in the semiconductor industry for its ability to create a system with heterogenous functionalities (Digital Logic/High-speed I/O etc. at its most efficient process node) hence improving overall silicon yield. This work presents a source- synchronous die-to-die I/O using a self-timed loop (behaviorally analogous to a gated ring oscillator) that generates high-speed edges, eliminating any power-hungry PLL/DLLs found in traditional die-to-die I/O interfaces. In addition, the proposed asynchronous architecture enables easy reconfigurability of data rates under a small form factor and efficient design-reuse. The scheme achieves a maximum of 4.8Gbps/wire at 0.4pJ/b generating an effective shoreline bandwidth of 1.47Tbps/mm.