An electrical study of differential clock die-to-die interconnection in multi-chip packages

摘要

This paper presents an electrical study on die-to-die interconnect, differential clock signals in MCPs. The paper seeks to tackle the issues caused by shorter and denser interconnection in combination with an ever-decreasing z-height profile. The proposed methods focus on buffer and channel design on existing or new signaling. Of note, they maintain a fair amount of design flexibility, while not jeopardizing overall margins. The methods primarily mitigate harmful ringing, ledge effects and excessively slow slew rates in the monotonic region in both MCP and discrete solutions. Ultimately, this translates into a shift in line with recent platforms' sleek and thin form factor and in turn, a cost saving benefit.