A 1.3 cycle lock time, non-PLL/DLL jitter suppression clock multiplier based on direct clock cycle interpolation for 'clock on demand'

摘要

A 1.3-cycle lock time, jitter suppression clock multiplier based on direct clock cycle interpolation uses an array of short-circuit-current-suppression interpolators. The circuits are verified in 622 MHz clock and data recovery satisfying the ITU-T G.958 jitter tolerance specification.