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Clock duty cycle based access timer combined with standard stage clocked output register
Clock duty cycle based access timer combined with standard stage clocked output register
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机译:基于时钟占空比的访问定时器,结合标准级时钟输出寄存器
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摘要
An output of an element under test is captured and stored, through a multiplexer, in a capture register. At a clock edge (either rising or falling edge) the element under test catches the “edge” and “strobes” the output. The multiplexer is strobed, and the delay and duty cycle are measured. Both the rising and falling edge are used as the timer.
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